PhD Engineering New College Grad

  • Full-time
  • Salary Range: 93,000.00-121,000.00
  • Business Function: Engineering
  • Work Location: San Jose Great Oaks Headquarters--LOC_WDT_USCA23

Company Description

The future. It’s on you. You & Western Digital.

We’ve been storing the world’s data for more than 50 years. Once, it was the most important thing we could do for data. Now we’re helping the world capture, preserve, access and transform data in a way only we can.

The most game-changing companies, consumers, professionals, and governments come to us for the technologies and solutions they need to capture, preserve, access, and transform their data.

But we can’t do it alone. Today’s exceptional data challenges require your exceptional skills. It’s You & Us. Together, we’re the next big thing in data. 
 
Western Digital® data-centric solutions are found under the G-Technology™, HGST, SanDisk®, Tegile™, Upthere™, and WD® brands.

Job Description

We are seeking highly motivated PhD candidates ready to apply their studies and contribute hands-on while working on our engineering teams. PhD candidate whose focus is towards, but not limited to, Electrical Engineering, Computer Engineering, Mechanical Engineering, Materials Science & Engineering, and graduated or are graduating from May 2020 to May 2022 are encouraged to apply. You will be considered for current and upcoming available new college grad roles.

 

We are recruiting for the following areas: 

·       Research & Design Hardware Development Engineering - The team is focused on developing new experiments from design to creation which will generate clear and actionable conclusions to guide the reliability improvement of Energy Assisted Magnetic Recording (EAMR) HDDs. In this role, you will develop novel instrumentation/ideas to evaluate thermal impacts on head/media components and interface material; participate and lead technical investigations from problem statement to conclusions; and liaise with the head/media component design team, modeling engineers, and HDD integration team to ensure a successful result.

  • Packaging Engineering - As a Packaging Engineer, you will work in the Packaging R&D group on the design of experiment and testing along with simulation across semiconductor packaging, flash memory product and host levels. In this position, you will be responsible for influencing package and product design by addressing the structural integrity and reliability issues in particular and advancing the technology of semiconductor packaging in general. The scope is to address all mechanical aspects of packaging technology and associated material and process interactions. The focus will be on solutions to meet increased demands for small form factor packages with thinner chips, denser interconnects and higher power. You will be responsible for the design of experiment and testing, and simulation as needed, of mechanical responses of IC package and flash products. This position will interface with package & product design, electrical and physical characterization, reliability testing, failure analysis, assembly R&D and other process teams. Solid background in applied mechanics, especially, experimental solid mechanics, is required. In-depth knowledge of IC packaging is highly desired.
  • Device Engineering – In this role, you’ll focus on electrical characterization of flash memory chips with the goal of improving the Reliability & Performance of the memory cell. Day-to-day responsibilities include, performing electrical measurements of various aspect of memory cell reliability such as endurance, data retention, program/read disturb etc. and compare it across device from different process conditions following by statistical data analysis; working at root cause analysis of physical mechanism of cell reliability degradation and identifying their solutions that may comprise of optimizing electrical operation of memory cell; as well as improvement of cell fabrication process.
  • Wafer Fabrication & Process Engineering -  Wafer Fabrication & Process Engineers will assume responsibility in the area of semiconductor process engineering and work directly on new process modules, including materials research, and developing new process integrations schemes for 3D NAND memory technology. Primary job function will focus on utilizing thin film processing techniques such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition/Etching (ALD/ALE), Reactive Ion Etching (RIE), Rapid Thermal Processing (RTP) and Oxidation to fabricate semiconductor memory devices. Process development will also include Research & Development on unique processes and materials. Collecting structural analysis such as SEMs/TEMs and analyzing many forms of process data from experimental splits using statistical analysis software and conducting process optimization using design of experiments (DOE) will be required.
  • Firmware Engineering – These candidates will develop embedded servo firmware for hard disk drives in the areas of servo loop design, optimization, calibration & actuator, spindle-motor control, etc. Responsibilities include, designing and implement Servo Loop design for hard disk drives; creating servo firmware development plans and schedules to meet deadline and development specifications; driving process / team / program changes and Influences team’s outcomes; participating product development in Servo Loop design, integration and drive level failure analysis; and working independently and cross-functionally with the ASIC, Mechanical, Channel FW, and CTLR FW teams.  

 

What is the LAUNCH Program? The LAUNCH Program is a supplemental, year-long program to introduce you into corporate insights and company culture. In this program, you will navigate through starting and launching your career towards your long-term aspirations. LAUNCH Program elements include:

  • Exposure to training opportunities
  • Comprehensive rewards & recognition insight
  • Professional insights from leaders and professionals
  • Engaging networking activities with cohort
  • Equity, Inclusion & Diversity and Global Giving & Doing events

 

Where are these roles located? You’ll have the opportunity to work with teams in:

  • Milpitas, California
  • San Jose, California

Qualifications

  • Strong area of study in, but not limited to, electronics, nanofabrication, signal processing, optics, machine learning & artificial intelligence
  • Focus in in HDD, flash, semiconductor, components, nonvolatile memory industry 
  • Effective in problem solving and communication with cross-functional teams  
  • Exceptional written and verbal communication skills
  • Proficient in Microsoft Office applications 
  • 3 or more publications in area of study desired

 

Additional Information

All your information will be kept confidential according to EEO guidelines.

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